Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads is required to transmit power, ground and input/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a high per chip yield.
A typical bonding pad structure consists of metal layers, emanating from the terminals of a chip device, separated by inter-metal dielectric (IMD) layers that are often silicon oxide. Metal vias pass through the IMD layers to connect the metal layers. Wires are bonded to a bonding metal pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and to provide scratch protection.
One mode of failure of the bonding pad relates to the peeling of the wire from the metal pattern due to forces exerted especially during the bonding process. Another failure mode that has been observed relates to bonding pad peel back, where forces imparted during wire bonding may cause a delaminating of one or more of the underlying layers. Another failure mode involves cracking of the IMD material.
A conventional bond pad 1 for an integrated circuit (IC) wafer is illustrated in FIGS. 1A and 1B. A pair of bond pad metal layers 2A, B are connected by an array of conductive vias 10. The bond pad metal layers 2A, B are separated by a layer of dielectric material 12, within which the vias 10 are disposed. During manufacturing, such as IC probe testing and during package assembly wire-bonding processes, external forces are applied to the bond pad 1. These forces may cause cracks 14 to form in the dielectric material 12 between the vias 10. Because the propagation path for these cracks 14 is largely uninhibited, the cracks 14 often extend to the area 16 outside the bond pad. Such cracking can cause current leakage, interlayer shorts, corrosion and reduced reliability of the IC. Moreover, large cracks 14 may cause failure of the IC very early in the life stage of the product in which the IC is used.
Thus, there is a need for an improved arrangement for metal vias that will minimize the chances for cracks to occur in the IMD, and where such cracks do occur, to minimize and/or limit their propagation. Such an arrangement should also be inexpensive to manufacture.